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Passive Voltage Divider: Seven R, C and L Topologies

Calculate unloaded output voltage magnitude and signed output phase for RR, CC, LL, RC, CR, RL and LR dividers, with preserved inverse controls and original connection references.

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How to use this calculator

  1. Enter the known values in the units shown. Results update as you type.
  2. Where results are editable, change one to solve backwards. Lock a value to hold it fixed.
  3. Use the worked example to check the method. Reset restores the starting fields.

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Formula and method

A 12 V input across a 1000 Ω upper resistor and a 2000 Ω lower resistor gives an unloaded output of 8 V across the lower resistor.

H=V₂/V₁=Z₂/(Z₁+Z₂), with ZR=R, ZC=1/(jωC), ZL=jωL and ω=2πf. RR: R₂/(R₁+R₂); CC: C₁/(C₁+C₂); LL: L₂/(L₁+L₂).

Worked example

Enter these known values and leave the other values blank.

Divider type
RR – Resistor + Resistor
Input voltage magnitude V₁
12 V
Resistance 1 (R==1==)
1000 Ω
Resistance 2 (R==2==)
2000 Ω
RR output voltage magnitude V₂
8 V

Assumptions and limitations

  • The first letter is the series element from V₁ to the output junction; the second is the shunt element from that junction to common ground. Output is measured across the second element. All seven original source choices are retained.
  • Voltage controls are nonnegative-amplitude magnitudes with strictly positive operating input and output in the finite component model. Phase is the argument of V₂/V₁: RC and LR outputs lag input, while CR and RL outputs lead input. The RR, CC and LL ratios are real and positive.
  • All component values are finite and strictly positive. The mixed-element modes use sinusoidal steady state with positive frequency. Ideal CC and LL ratios cancel frequency for nonzero AC frequency; they do not model DC capacitor charging, initial conditions, mutual inductance or parasitic losses. The RR relation also applies to a positive DC input.
  • The output is open-circuit apart from the displayed lower element. A finite load changes the lower impedance and output voltage; this calculation does not include that load or a finite source impedance.
  • For these exact topologies, output magnitude is strictly below input for finite positive components. Magnitude-only inverse controls use the captured positive-component branch. The two mixed-element phase limits at zero and ±90° require zero, infinite or otherwise limiting parameters; rounded boundary results are withheld when outside the model’s resolution.
  • The angular-frequency selector retains the source’s rounded Hz↔rad/s coefficient (relative error below 10⁻²⁰). Use direct rad/s or the separate cyclic-frequency Hz control when comparing the two quantities.
  • Controls use bounded exact finite-decimal preflight. Nonzero input values below 10⁻¹⁰⁰⁰⁰ in equation base units are unsupported. Arithmetic uses 64 significant digits; tiny supported outputs use scientific notation and unrepresentable or zero-losing unit conversions are withheld with an error. Near a singular inverse or attenuation/phase limit, extra digits in the physical inputs may exceed the computation’s resolution.
  • Near unity gain, magnitude inverses use a factored voltage difference of squares. Inward voltage-unit conversions must preserve the exact decimal significand; a conversion that drops significant digits is withheld before solving. Use native volts or fewer significant digits. This does not extend the64-digit arithmetic precision.

Common questions

Which component is the output measured across?

The second component in the selected pair. In RC mode that is the capacitor; in CR mode it is the resistor. The connection reference marks the common ground and output junction.

Why does the capacitive divider use C₁ in the numerator?

Capacitive impedance is inversely proportional to capacitance. Substituting Z=1/(jωC) into Z₂/(Z₁+Z₂) gives C₁/(C₁+C₂). Output remains measured across C₂.

Can I use a negative output phase?

Yes. The RC and LR modes have negative output phase relative to input. CR and RL have positive phase. Supply a phase consistent with the selected circuit and clear the quantity you want the inverse to solve.

References

Factor the exact positive voltage difference of squares as (V1−V2)(V1+V2) before square root and division in all six affected RC/LR magnitude inverse branches. This preserves the captured positive branch while avoiding cancellation in (V1/V2)^2−1 and V1^2−V2^2 near unity gain. All seven topologies, twelve identities and fifty directions remain. Preserve the literal original28condition array and all50rule directions. Correct RC/LR phase sign predicates to their actual negative atan equations; all other original positive predicates use exact mathematically equivalent sign expressions. Add explicit passive attenuation and finite principal-phase domains tied to each source control.

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