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DDR CAS Latency in Nanoseconds

Convert CAS cycles and DDR transfer rate in MT/s to the modeled CAS delay in nanoseconds, or solve either input.

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How to use this calculator

  1. Enter the known values in the units shown. Results update as you type.
  2. Where results are editable, change one to solve backwards. Lock a value to hold it fixed.
  3. Use the worked example to check the method. Reset restores the starting fields.

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Formula and method

DDR memory at 6,000 MT/s with CL30 has a modeled CAS delay of 30 × 2,000 / 6,000 = 10 nanoseconds.

CAS delay (ns) = CAS cycles × 2000 / data rate (MT/s)

Worked example

Enter these known values and leave the other values blank.

DDR transfer rate
6000 MT/s
CAS latency in clock cycles
30
Modeled CAS delay
10 nanoseconds

Assumptions and limitations

  • Enter the double-data-rate transfer rate in MT/s, not the underlying memory clock in MHz. DDR transfers data twice per clock cycle.
  • This is the CAS portion of access delay under the model. It excludes other memory timings, controller delays, cache misses, queues and system workload effects.
  • The inputs must be positive. Fractional cycle values are accepted as mathematical inputs; use supported timings for the actual memory configuration.

Common questions

Why does the formula use 2000?

The transfer rate is twice the clock rate, and converting a million cycles per second to nanoseconds contributes a factor of 1000.

Does a lower result guarantee a faster computer?

No. It compares this timing component only. Bandwidth, other timings, memory capacity and workload also matter.

References

The calculation equations, inverse formulas, units, and input rules were imported from this source. Bookify provides the interface and equation solver.

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